CLA-based sine/cosine add-on for the existing IEEE-754 multiplier.

Files:
- design.sv: unchanged original multiplier from the supplied project
- fp_sincos_cordic.sv: Q4.28 CORDIC, 24 unrolled stages, each using your existing cla_generic 3 times
- fp_calc_sincos_top.sv: select multiply/sine/cosine
- tb_fp_sincos.sv: basic testbench

Operation selector: 00 multiply a*b; 01 sin(a); 10 cos(a); 11 quiet NaN.
Angles are in radians and limited to approximately +/-2*pi.
Educational combinational approximation, not fully IEEE-754-correct.

Compile together (do not separately include design.sv twice):
iverilog -g2012 -s tb_fp_sincos -o sim.vvp design.sv fp_sincos_cordic.sv fp_calc_sincos_top.sv tb_fp_sincos.sv
vvp sim.vvp

IMPORTANT: The original design has a *binary* CLA, not a complete floating-point adder.
CLA adds the signed Q4.28 CORDIC values as 32-bit two's-complement integers.
The FP32<->Q4.28 conversion is still necessary.
SystemVerilog simulation was not run in this environment (Icarus/Verilator unavailable).
